1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor package technology, and more particularly to a stack package of a ball grid array type.
2. Description of the Related Art
Stacking technology may be implemented as a method to improve the degree of integrity in a package assembly process. Stacking technology may be classified into chip stacking methods and/or package stacking methods. Package stacking methods may, as the name implies, involve stacking packages. The chips of the packages may be inspected for electrical characteristics and/or may be verified for reliability in a package state (e.g., before assembling the packages in the stack). Accordingly, package stacking methods may provide advantages in reliability and/or yield compared to chip stacking methods.
FIG. 1 is a schematic sectional view of a conventional stack package 10. The stack package 10 may include a stack of individual packages of a ball grid array (“BGA”) type. A package stacking method may be implemented to assemble the stack package 10. As shown in FIG. 1, the conventional BGA stack package 10 may be fabricated by stacking an upper package 11b on a lower package 11a through conductive bumps 12. The conductive bumps 12 may be disposed at the edge portion of the lower package 11b. 
Although the conventional stack package 10 is generally thought to provide acceptable performance, it is not without shortcomings. FIG. 2 shows types of defects that may occur in the conventional stack package 10.
For example, the individual packages 11a and 11b may become warped due to the configuration of the individual packages themselves. Such warpage may causes defects in a stacking process and/or low reliability, for example. Each individual package 11a and 11b may have a circuit substrate 14 that may be attached to a surface of a semiconductor chip 13. Thus, the upper and the lower surfaces of each individual package may be dissimilar in configuration and/or material. As a result, warpage may occur due to differences in the coefficients of thermal expansion during various heat-accompanied processes (for example). The warpage phenomena of the individual packages 11a and 11b may cause a defect 21 in which a conductive bump 12 becomes separated from an adjacent package, and/or solder joint cracks 22, for example.
The conventional stack package 10 may have a configuration by which a rear surface of the semiconductor chip 13 may be exposed outwards. Accordingly, the semiconductor chip 13 may experience breakage defects 23 induced by external shock.
A BGA package may have a standard conductive bump layout. However, when the same kinds of packages are stacked according to the conventional technology, the lowermost package 11a may not have the standard conductive bump layout. If the lowermost package 11a has a different conductive bump layout, a yield of the stacking process may decrease.